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Aldec Releases ALINT 2008.10 supporting Mixed VHDL and Verilog Design Rule Checking
Aldec, Inc., a 24 year old EDA company, announced today the release of ALINT 2008.10, a VHDL and Verilog Design Rule Checking Tool used to analyze HDL source code against a comprehensive set of ASIC design guidelines for early bug detection.
ALINT reduces risk when developing complex multi-million gate ASICs by resolving structural, coding and consistency problems early in the design cycle.
ALINT 2008.10 delivers support for VHDL, Verilog...
preview:
http://www.aldec.com
date: 12/9/2008
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