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An ESL Methodology for Functional Verification between Untimed C++ and RTL using SystemC
Many RTL designs are developed from C++ algorithms that have been extensively tested using a C++ testbench.
The C++ testbench often represents a huge engineering effort to provide as much coverage of the algorithm as possible.
Once the algorithm has been synthesized to RTL, however, a new testbench is typically written instead of using the original C++ testbench.
This creates a discontinuity between the verification performed on the...
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Creating a Consistent Verification Environment from Algorithm to RTL
Hardware implementations of DSP designs typically start out as algorithms modeled in tools like Matlab(tm). Such tools provide a natural representation of the algorithm and an extensive collection of building blocks used to analyze algorithm performance, both quantitatively (S/N, BER, quantization errors, etc) and qualitatively (spectrum displays, processed image viewing, etc). They can also provide a quantitative analysis of possible fixed...
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DO-254 Compliance: Reducing Project Cost by Avoiding Common Pitfalls
Many folks stumble on very similar issues when they begin their journey towards creating and executing DO-254 compliant design projects.
The good news is that each of these issues has solutions.
Understanding these common pitfalls, and proactively addressing them before they cost a project time, resource and certification risk, is essential.
Some of these common pitfalls, along with advice for addressing them (based on learnings from...
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Executive Presentation - Meeting the Critical Challenges of IC Implementation
At the 2008 Design Automation Conference in June, Joseph Sawicki, vice president and general manager of the Design to Silicon Division, laid out Mentor’s strategy to help customers with the challenges they face with IC implementation as they move to smaller process nodes.
Sawicki discusses new technology acquisitions and developments, product enhancements, and organizational alignment.
He also describes how Mentor is driving toward the...
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Physically Aware Synthesis
Traditional physical synthesis techniques rely on lengthy place-and-route iterations to achieve good quality of results (QoR). Newer routing-centric approaches suffer from very long run times and limited device support while post-placement-centric physical synthesis provides only limited QoR improvements.
To address these issues, a unique and innovative pre-place-and-route, physically-aware synthesis based on the concept of statistical...
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RTL Analysis and Creation using Spreadsheets
Today millions of users depend on spreadsheets, the most popular being Microsoft Excel, to organize, manage, analyze, model and generate numerical and text data.
Spreadsheets are now making their way into hardware design.
This paper covers the details of using the Interface Based Design (IBD) editor provided by Mentor Graphics HDL Designer Series(tm) to develop spreadsheets for hardware design.
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paper
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Mathworks - Free Simulink ROI Kit
Return on Investment in Simulink® for Electronic System Design' is now available from Mathworks.
Authored by Dr. Handel Jonesl, the white paper details significant time and cost savings that companies are realizing by incorporating Model-Based Design, specifically with the Simulink product family, into their electronic system design flow.
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