 
60% Savings on SHARC Processor Development Tools
For a limited time, you can purchase a SHARC development tools bundle at a 60% savings.
The bundle includes VisualDSP++ Development Software and the High Performance USB-based Emulator.
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for purchasing details.
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tutorial
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A Tutorial on Convolutional Coding with Viterbi Decoding
This tutorial iintroduces the reader to a forward error correction technique known as convolutional coding with Viterbi decoding.
The page is equipped with definitions of the mathematical algorithms and C source examples.
preview:
http://pweb.netcom.com
date: 1/1/2002
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tutorial
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Adaptive Signal Processing JAVA Applet
This site contains a tutorial on adaptive signal processing, including noise cancellation, system identification and prediction.
A Java applet is provided to illustrate the concepts interactively.
preview:
http://www.eee.strath.ac.uk
date: 1/1/1999
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tutorial
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Algorithms for programmers ideas and source code (Free eBook)
This is a draft of a text about selected algorithms.
The audience in mind are programmers who are interested in the treated algorithms and actually want to create and understand working and reasonably optimized code.
The style varies somewhat which I do not consider bad per se: While some topics (as fast Fourier transforms) need a clear and explicit introduction others (like the bit wizardry chapter) seem to be best presented by...
preview:
http://www.jjj.de
date: 3/1/2006
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sbc
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X5-210M
The X5-210M is an XMC IO module featuring four 14-bit 250 MSPS A/Ds with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface.
A Xilinx Virtex5 SX95T with 512MB DDR2 DRAM and 4MB QDR-II memory provide a very high performance DSP core for demanding applications such as emerging wireless standards.
The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates exceeding 300 GMACs per second.
preview:
http://www.innovative-dsp.com
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sbc
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X5-400M
PCIe XMC Module - Two 400 MSPS, 14-bit TI ADS5474 ADCs and Two 500 MSPS, 16-bit DACs, Virtex5 FPGA and 512 MB Memory.
The X5-400M is an XMC IO module featuring two 14-bit, 400 MSPS A/D and two 16-bit, 500 MSPS DAC channels with a Virtex5 FPGA computing core and PCI Express host interface on a standard XMC module.
A Xilinx Virtex5 SX95T FPGA with 512 MB DDR2 DRAM and 4MB QDR-II memory provide a very high performance DSP core for demanding applications such as emerging wireless standards.
The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates exceeding 300 GMACs per second.
preview:
http://www.innovative-dsp.com
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project
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Haskell DSP Libraries
The project is an implementation of DSP and related algorithms in the programming language Haskell.
preview:
http://sourceforge.net
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project
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SPIRAL Project
The goal of SPIRAL is to automate the process of implementation, optimization and platform adaptation of DSP algorithms.
In the following we give a brief overview on our approach to achieve this goal.
For more detailed information, please visit our publications section.
preview:
http://www.ece.cmu.edu
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